1. general description the 74hc03-q100; 74hct03-q100 is a quad 2-input nand gate with open-drain outputs. inputs include clamp diodes that enabl e the use of current limiting resistors to interface inputs to vo ltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? input levels: ? for 74hc03-q100: cmos level ? for 74hct03-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 74hc03-q100; 74hct03-q100 quad 2-input nand gate rev. 1 ? 4 july 2013 product data sheet table 1. ordering information type number package temperature range name description version 74hc03d-q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74hct03d-q100 74HC03DB-Q100 ? 40 ? c to +125 ? c ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74hct03db-q100 74hc03pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74hct03pw-q100
74hc_hct03_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 4 july 2013 2 of 14 nxp semiconductors 74hc03-q100; 74hct03-q100 quad 2-input nand gate 4. functional diagram 5. pinning information 5.1 pinning 5.2 pin description fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) mna212 1a 1y 1b 1 2 3 2a 2y 2b 4 5 6 3a 3y 3b 9 10 8 4a 4y 4b 12 13 11 d d d 001aab715 y gnd a b fig 4. pin configuration so14 fig 5. pin configuration (t)ssop14 + & |